FIELD OF THE INVENTION
The present invention relates to an instruction decoding mechanism for reducing the execution time of a microprocessor, and more particularly, to a mechanism for reducing execution time of a microprocessor during addresses decoding by means of earlier detection, and the subsequent replacement, of indirect addresses with direct addresses.
According to the conventional addressing method of a microprocessor, the indirect addressing method thereof is to be done by using an indirect register (such as an index register) and a data register (such as a data block register) to obtain an actual address for instruction decoding. The actual address is substantially the sum of the implied value of the data register and the value stored in the indirect register. Therefore, when performing data access, some storage space in the data register must be taken, and a considerable time will be wasted.
The indirect address register and the virtual addressing approach are derived from the known method of memory mapping I/O, and may be applied to various functional registers, such as a timer/counter, an interrupt control register, and an I/O register. The mapping method is widely used in various commercially available microprocessors, such as Motorola M68000 series and Intel 8051 series microprocessors. Particularly, such method is mostly used in the microcontroller for control purpose, and its advantages are as follows:
(1). When a register address uses a memory address, no additional circuit upon designing a special register is required for decoding operation; i.e., it requires only the circuit of the original memory for decoding without having to provide additional instruction and instruction-decoding circuits. Therefore, such method can simplify the IC considerably.
(2). In a micro-controller and a micro-processor, there are more operation requirements to the aforesaid special register. For example, when a bit data operation for an I/O port is executed, such as setting or clearing the data of a bit, such circuits used in the special register and the memory may only be used for the special register, which will limit the functions of the system. On the contrary, if the special register and the memory address are used together, the efficiency and the functions of the system may be increased considerably.
FIG. 1 is a timing sequence according to the prior art decoding method. The conventional processes mainly includes steps of a fetching cycle, a decoding cycle, and an executing cycle in sequence. The fetching cycle is indicated by FETCH, the decoding cycle is indicated by DECODE, and the executing cycle is indicated by EXECUTION.
In the fetching cycle, the instruction code is read at first. The instruction code or operation code is a portion of a machine language or assembly language instruction that specifies the type of the instruction (that is, what kind of operation the instruction performs) and the structure of the data upon which it operates.
The fetched instruction code is decoded by either direct addressing mode or indirect addressing mode. In the indirect addressing operation mode, the real address is necessary to be further counted. The execution cycle includes steps of reading register value, performing operation, and writing back the data to the register.
As described above, the instruction decoding cycle may be achieved either by direct addressing mode or indirect addressing mode. Typically, the instruction decoding operation may be completed by means of the pipeline decoding approach. The operation of the pipeline decoding approach may be performed by two types as follows:
______________________________________ Type I: ______________________________________ .vertline. FETCH .vertline. DECODE+ .vertline. EXECUTION .vertline. FETCH .vertline. DECODE+ .vertline. EXECUTION ______________________________________
In the above case, the time required for DECODE and EXECUTION will limit the functions of the micro-processor.
______________________________________ Type II: ______________________________________ .vertline. FETCH+ .vertline. EXECUTION .vertline. DECODE .vertline. FETCH+ .vertline. EXECUTION .vertline. DECODE ______________________________________
In this later case, all signals after DECODE must be recorded for EXECUTION use.
The conventional addressing mode and the instruction operation method usually can provide a powerful function; the circuit required by a more complex instruction would be more difficult to design, and would require longer designing time. In other words, it would be much difficult to use the Pipeline and Super scale technique to increase the functions. Therefore, an idea of RISC (Reduced Instruction Set Computer) has been proposed so as to cause the instructions of complex functions to be divided into the most simple instructions by means of statistics and analysis. Because of simplicity, such configuration can provide a higher efficiency, can be modified easily, and can be arranged in a regular order. Therefore, the pipeline and super scale technique can be used easily to provide a higher function.
The present invention is deemed to conform to the aforesaid simplicity in terms of changing instructions, i.e., the time sequence order can easily be used for the pipeline technique to increase the efficiency of the system. The aforesaid advantages cannot be provided by the conventional instruction decoding; such replacing method is deemed having industrial value in the field of developing high-efficiency microprocessor.